Natural Science Forum / Physics / General Physics / August 2008

On Aug 28, 11:48 pm, falder...@yahoo.co.uk wrote:

image seardh: "de morgan's theorem"

http://images.google.com/images?hl=en&safe=off&resnum=0&q=de%20morgan's%20theore
m&um=1&ie=UTF-8&sa=N&tab=wi

Notice the open circles are inverters.

Both are better than your reading skills.

Remedial Reading Strategies & Reading Intervention Program
http://www.readkwik.com/

Sue...

On Aug 28, 11:48 pm, falder...@yahoo.co.uk wrote:

Correct assessment.   [Especially the assessment of Sue's knowledge of
physics.] Although nobody has bothered to explain how this works yet.
(or don't know!)

Sue is a moron. She pretends to be "intellectual" but has exactly ZERO
knowledge of technology. All she does is make mathematical comments
that have no relevance to physics or other practical matters.  About
all she's good for is "plonking".

For those with actual inquiring minds DeMorgan's Theorem is to show
the equivalence between a Nand gate and an Or gate with inverted
inputs. The latch in question is implemented with Nor gates.
DeMorgan's Theorem states it can also be implemented with Nand gates
as Falder notes and has absolutely NOTHING to do with the question as
posed. Sue just wanted to show everybody she's heard of DeMorgan's
Theorem.  Sorry, not impressed.

The latch in question can easily be understood if you assume that the
output is either 1 or 0 and both inputs are 0. You will notice that in
either case the arrangement is stable and the output stays in the
state you assumed. (hint: it's a memory!)  Now if you take ONE of the
inputs and make it go high you discover that one of the inputs makes
the output go high (or stay high if it's already there) and the other
makes it go low (or stay low if it's already there). When both inputs
return to 0 the output stays (memory) in the state you changed it to.

As Andro notes it's often used for "switch debounce". Imagine what
happens to the output if you drive a given input high multiple times?
(as when switch contacts "bounce")  Hint: the first high switches the
latch and then after that the memory keeps it that way no matter how
many times the input goes up and down.

Also a careful examination of the latch circuit shows it has not only
two stable states but also a third unstable one that the latch goes
through when cleared from one state to the other. As a result of this
the rise and fall of the latch is set by the delay time of the gates
rather than risetime of the input signals.

Hey Sue, are you EVER going to give up the bullshit and start learning
some REAL science?

On Aug 30, 6:36 pm, patrol_b...@hotmail.com wrote:

Search: "logic family" pull up.

http://www.google.com/search?hl=en&safe=off&pwst=1&sa=X&oi=spell&resnum=0&ct=res
ult&cd=1&q=%22logic+family%22+pull+up&spell=1

Sue...

On Aug 29, 2:55 pm, "Michael J. Strickland"
<qualityservic...@verizon.net> wrote:

Yes, that's helpful, thanks. Now I see that you don't necessarily have
to supply voltage to *both* inputs; you are free to supply only to one
input. Still, I'm a bit uncertain on a related point that maybe you or
someone else can clear up.

Is the following true?:

For NOT, NAND, and NOR gates, 0 must mean low voltage, but for AND and
OR gates, 0 can mean either low voltage or no voltage. Thus, for
example, a NOT gate turns a low voltage into a high voltage (and vice
versa), but will not change *no* voltage into high voltage (or vice
versa). And, for example, an OR gate will turn a low voltage and a
high voltage into a high voltage, but will also turn a *no* voltage
and a high voltage into a high voltage?

For anyone interested, my reasoning behind this statement is detailed
below:

I've been reading that, in modern terms, the "1s" and "0s" are usually
abstract representations of high and low voltages respectively. For
example, an inverter (NOT gate) will change a low voltage to a high
voltage and vice versa. The point is, 0 does *not* mean *no* voltage,
but low voltage. For if it meant no voltage, then that would mean that
a NOT gate would somehow magically convert no voltage into high
voltage, *even if the logic circuit was not supplied any
electricity*!!! However, there's perhaps a bit of a contradiction to
this. In the flip-flop example I was originally asking about, if you
supply a high voltage to the top input, the output to the OR gate will
be a high voltage, *even though its other input wire has *no* voltage
(not low voltage) going through it. Therefore, in this instance, 0
really does seem to represent no voltage. Thus, depending on context,
0 can represent either low voltage or no voltage. For NOT, NAND, and
NOR gates, 0 input must mean low voltage, but for AND and OR gates, 0
input can mean either low voltage or no voltage.
================================================

  http://www.imodelit.com/admin/files/CMOS_Transistor_Inverter.gif

If the top transistor is "on" and the bottom one "off", the output is high.
If the top transistor is "off" and the bottom one "on", the output is low.
If the top transistor is "on" and the bottom one "on",  we have a bad
device, a short circuit.
If both are "off" then the output is floating and we can connect another
device to the same output bus.

So.... by connecting a lot of identical circuits (cells) to the same output
and enabling just one of them, we have an addressable array that we
call "RAM"  (random access memory). Your computer has an address
bus which selects the device and a data bus which "reads" (and writes)
the output of one cell at a time.

So the inputs to one of these
  http://mrg.ee.uwa.edu.au/websiteCopy/images/cmosImager.jpg
are:

some number of address lines ( the address bus)
some number of data lines  (the data bus)
enable (to connect the device  to the data bus)
read   (get the data out)
write  (put new data in)

On Aug 30, 6:36 pm, patrol_b...@hotmail.com wrote:

What you say may or may not be true. But generally you have to define
what you mean by "no voltage".  The bottom line goes like this. Logic
gates are constructed with certain circuits. These circuits vary but
are all the same in a given "logic family". Within a given "logic
family" all the circuits if not quite the same are at least arranged
so that the specification as to what constitutes a "0" and what
constitutes a "1" is the same for all gates and devices.  This is
necessary because all the packs in the family are required to work
with all other packs. The only exception is with "drivers" which are
designed to run other electronic devices rather than other logic packs
(gates etc.) and "translators" designed to connect to a different
logic family.

But the specification as to what a given "family" defines as a "1" and
a "0" varies widely.  Usually each is defined in terms of a voltage
range and/or a current range for each state. Often only one or the
other is important. For example in CMOS families next to no current is
drawn and "0" is specified by being below a given voltage and "1" by
being above another voltage (often specified as a percentage of supply
voltage).

So now we get to your question about "no voltage". So what exactly do
you mean by that? If you mean zero volts, then for some families that
means a "0" as it's below the spec for that state.  In others it might
not. It all depends on the definition for the given logic circuits.
On the other hand you might mean that "no voltage" means the wire is
disconnected. So what does that do?  Again it depends on the family
and how they are wired. If the family is CMOS, the input is a very
high impedance so disconnecting just leaves the input "floating" which
means it simply takes what ever voltage it had when you disconnected
it or whatever static charge it collected. Basically "disconnected" is
undefined for that family.  TTL family on the other hand has all
inputs going to the emitter of transistors.  Because of this, "zero
volts" would represent a "0" while if you disconnected the input wire,
the emitter would be forced to some voltage and the gate would see
this as a "1".  So the answer to your question is "it depends" and you
really need to specify more to get an exact answer. There are lots of
logic families out there. Some old and obsolete and no longer used,
and others new and very fast and in common use. Some are sort of in
between used to translate between old and new.

And it gets still better. Take the "undefined" CMOS case. Suppose
you'd like to have the logic state defined when an input is
disconnected. All you need to do is add a resistor from the input to
the supply voltage (this resistor is called a pull-up resistor as it
pulls the voltage up to a "high" or "1" level) and any disconnect of
the input becomes a "1". The resistor is of a high enough value that
it doesn't have an effect upon any gate output you might connect to
this input.  You can do the same thing with a "pull-down" resistor
wired to ground (zero volts) only now a disconnect becomes a low or
"0". You can't use both a pull-up and pull-down at the same time.
(tell me why?)  On the other hand, the matter is even more complicated
than this because whether or not you can use either a pull-up or a
pull-down depends on the circuits of the given logic family of
interest.  But usually these things are of no consequence because so
long as you always drive inputs with the outputs of other gates you'll
have no need to deal with a "disconnected" state. It's only at the
inputs and outputs to your logic device where one needs to deal with
the specifications for "1" and "0" in some manner.  Just as you'll
find there are special logic devices (drivers) designed to drive
output devices other than other gates, there are also input "buffers"
designed to deal with voltage ranges outside of the usual logic
specifications.

OK?

While what you are learning is basic and good, today most logic
systems tend to be done with programmable logic arrays. These are
devices with a lot of inputs and outputs (specified to match a given
logic family). inside they have a large array of gates and other logic
functions that can be "wired" in various ways through a programming
procedure. This means you end up with a custom "circuit" that gives
you the logic equations you need for whatever you are doing. But all
this is a something of a step up from where you are right now.

Hope this helps.